The present invention relates generally to electronic circuit designs, and, more particularly, to a method for scan chain re-ordering in electronic circuit designs.
Electronic design automation (EDA) tools are widely used to design systems-on-a-chip (SoC). Designing an SoC includes preparing a layout/floor plan for various circuit components, including standard cells, of the SoC. The layout plan is prepared while optimizing several placement objectives, viz., total net-length, timing, congestion, power, and placement runtime minimization. Minimizing the total net-length of the various standard cell nets is a key objective of a layout plan because it helps to ensure minimum die area, power consumption, and signal delays. Additionally, EDA tools ensure that the total net-length is optimized to prevent congestion in the SoC layout plan.
EDA tools further optimize connections of scan-nets that form scan chains in conjunction with standard cells. The scan-nets are optimized using various algorithms including horizontal, vertical, and minimum-net-length algorithms to meet the placement objectives.
However, conventional EDA tools do not facilitate ‘region-based’ scan chain reordering. ‘Region-based’ scan chain reordering is useful in relieving congestion in layout plans that include specific regions with congestion in one direction, either vertical or horizontal. Further, conventional EDA tools do not facilitate ‘partial scan chain reordering’, i.e., reordering multiple portions of a scan chain (scan chain segments) in horizontal or vertical directions based on a type of congestion (horizontal or vertical) occurring in a region of the layout plan with which the scan chain segment is associated.
Therefore, it would be advantageous to have an EDA tool that facilitates region-based scan chain reordering and partial scan chain segment reordering and that overcomes the above-mentioned limitations of existing EDA tools.